Semiconductor memories, especially high-density semiconductor memories such as Static Random Access Memory (SRAM) utilizing small device geometries, generally incorporate sense amplifiers to provide the output drive capability for memory reads. Each sense amplifier detects the differential voltage across a corresponding pair of complementary bit lines (BL and BL′) in an SRAM array. Outputting correctly sensed bit data from the memory array is important for data integrity, access speed, power consumption, etc., and depends on a number of process-related and environmental variables.
FIG. 1 illustrates a portion of an example memory device 100. Memory device 100 includes one or more memory arrays 102 (only one of which is shown). Each memory array 102 includes a plurality of memory cells 104 arranged in a plurality of rows and a plurality of columns, each row corresponding to a word line WL (WL0, WL1, . . . ) and each column corresponding to a pair of complementary bit lines, BL and BL′ ((BL0, BL′0), (BL1, BL′1), (BL2, BL′2), etc.). A word line decoder 106 receives word line address signals (“WL ADDR”) and provides word line signals to select one of word lines WL of memory array 102. A bit line decoder 108 receives bit line address signals (“BL ADDR”) and provides bit line signals Y (Y0, Y1, Y2, etc.) to select a pair of bit lines BL and BL′ of memory array 102 through switches 110. Each switch 110 may comprise a pair of NMOS transistors, for example, and is turned on and off by bit line signals Y. Each memory cell 104 may be selected by selecting the corresponding word line and pair of bit lines. A sense amplifier 112 is coupled to bit lines BL and BL′ to detect the bit stored in the selected memory cell 104 and to output the same. A control signal CTRL is provided to word line decoder 106 and the sense amplifier 112 as a clock signal to trigger their respective operations. For example, on an edge (rising edge or falling edge) of control signal CTRL, word line decoder 106 may decode the word line address and the sense amplifier 112 may detect a bit stored in a selected memory cell 104 and output the same. Memory device 100 also includes a plurality of precharging PMOS transistors 114 each coupling a corresponding bit line BL or BL′ to a power supply voltage VDD to precharge the corresponding bit line BL or BL′, thereby increasing the speed in accessing memory cells 104.
Memory cells 104 may comprise any suitable structure, such as a conventional 6-transistor structure shown in FIG. 2. FIG. 2 shows one memory cell 104 including two PMOS transistors 202 and 204 and four NMOS transistors 206, 208, 210, and 212. Each of the MOS transistors 202, 204, 206, 208, 210, and 212 has a gate, a source, and a drain. The gate of PMOS transistor 202, the gate of NMOS transistor 206, the drain of PMOS transistor 204, the drain of NMOS transistor 208, and the source of NMOS transistor 212 are all coupled to one another. The gate of PMOS transistor 204, the gate of NMOS transistor 208, the drain of PMOS transistor 202, the drain of NMOS transistor 206, and the source of NMOS transistor 210 are also all coupled to one another. The sources of PMOS transistors 202 and 204 are coupled to the power supply voltage VDD. The sources NMOS transistors 206 and 208 are grounded to VSS. The gates of NMOS transistors 210 and 212 are coupled to receive the word line signal WL. The drain of NMOS transistor 210 is coupled to the bit line BL. The drain of NMOS transistor 212 is coupled to the bit line BL′. Thus, PMOS transistor 202 and NMOS transistor 206 form an inverter 214, and PMOS transistor 204 and NMOS transistor 208 form an inverter 216. Inverters 214 and 216 are coupled to form a loop and may stably store a bit or other unit of data. If the drains of PMOS transistor 202 and NMOS transistor 206 are at a logic high, i.e., approximately VDD, then the drains of PMOS transistor 204 and NMOS transistor 208 are at a logic low, i.e., approximately VSS, and memory cell 104 is considered to have stored a logic high bit. If the drains of PMOS transistor 202 and NMOS transistor 206 are at logic low, then the drains of PMOS transistor 204 and NMOS transistor 208 are at logic high, and memory cell 104 is considered to have stored a logic low bit. When NMOS transistors 210 and 212 are turned on by word line signal WL, the bit stored in memory cell 104 and its reverse respectively appear on corresponding bit lines BL and BL′.
FIG. 2 also shows two of precharging PMOS transistors 114, shown as 114a and 114b, each having a gate, a drain, and a source. The gates of precharging PMOS transistors 114a and 114b are coupled to receive control signal CTRL. The sources of precharging PMOS transistors 114a and 114b are coupled to power supply voltage VDD. The drain of precharging PMOS transistor 114a is coupled to bit line BL. The drain of precharging PMOS transistor 114b is coupled to bit line BL′. Switch 110 is shown to include NMOS transistors 218 and 220, each having a gate, a drain, and a source. The gates of NMOS transistors 218 and 220 receive bit line signal Y from the bit line decoder 108 (not shown). The drain of NMOS transistor 218 is coupled to bit line BL. The drain of NMOS transistor 220 is coupled to bit line BL′. The sense amplifier 112 is coupled to the sources of NMOS transistors 218 and 220. Thus, when one memory cell 104 is selected, corresponding NMOS transistors 218 and 220 are turned on, corresponding NMOS transistors 210 and 212 are also turned on, corresponding PMOS transistors 114a and 114b are turned off, and the sense amplifier 112 is allowed to access the bit stored in the selected memory cell 104 through corresponding bit lines BL and BL′. Then, on an edge of control signal CTRL, the sense amplifier 112 is triggered to detect voltages on bit lines BL and BL′, amplify a differential voltage across bit lines BL and BL′, and output the amplified differential voltage.
Due to parasitic resistances and capacitances, bit lines BL and BL′ corresponding to the selected memory cell 104 do not instantly exhibit the bit stored in the selected memory cell 104. Rather, if the bit stored in the selected memory cell 104 is a logic low, the corresponding bit line BL is gradually discharged from a precharged logic high state to a logic low state. Conversely, if the bit stored in the selected memory cell 104 is a logic high, the corresponding bit line BL′ is gradually discharged from a precharged logic high state to a logic low state. A read margin is the differential voltage across the corresponding pair of bit lines BL and BL′ when the sense amplifier 112 is triggered to detect the voltages on bit lines BL and BL′. Because the sense amplifier 112 can only detect a differential voltage above a certain level, e.g., 100 mV, a small read margin, if below that certain level, may result in a read failure. To avoid a read failure, it is desirable to delay the triggering of the sense amplifier 112 to allow the differential voltage across bit lines BL and BL′ to develop and exceed the detectable level of the sense amplifier 112, i.e., to ensure a read margin exceeding the detectable level of the sense amplifier 112. One technique for delaying the triggering of the sense amplifier 112 is to use a tracking circuit, a conventional example of which is shown in FIG. 3.
In FIG. 3, a tracking circuit 302 is shown to include a pair of dummy bit lines DBL and DBL′ and several tracking cells 304. A conventional tracking circuit, such as tracking circuit 302, may include one or more tracking cells 304. Tracking circuit 302 receives and delays control signal CTRL. A control circuit 306 is coupled between tracking circuit 302 and the sense amplifier 112 for receiving the delayed control signal CTRL and generating a clock signal for the sense amplifier 112. An example of control circuit 306 is an inverter that simply inverts the delayed control signal CTRL. FIG. 3 shows that dummy bit line DBL is coupled to power supply voltage VDD through a precharging PMOS transistor 308.
FIG. 4 shows the detailed structure of an example tracking cell 304, which includes six transistors, i.e., PMOS transistors 310 and 312 and NMOS transistors 314, 316, 318, and 320. With reference back to FIG. 2, it can be seen that tracking cell 304 has a structure similar to memory cell 104, except that the gates of PMOS transistor 310 and NMOS transistor 314 are coupled to power supply voltage VDD, and that the gate of NMOS transistor 318 is coupled to control signal CTRL. Also as shown in FIG. 4, dummy bit line DBL′ is floating and not used, while dummy bit line DBL is coupled to the sense amplifier 112 through control circuit 306 for generating the clock signal for the sense amplifier 112. For reasons that will become clear below, in some conventional designs only the NMOS transistor 318 (sometimes referred to as the n-channel pass-gate) and the PMOS transistor 314 (sometimes referred to as the pull-down transistor) are retained, with the PMOS transistors 310 and 312 and the NMOS transistors 316 and 320 being omitted.
When memory array 102 is not accessed, control signal CTRL is at logic 0, and dummy bit line DBL is pre-charged to a voltage level approximately equal to VDD. When a memory cell 104 of memory array 102 is being accessed, control signal CTRL changes to logic high, turning off PMOS transistor 308 and turning on NMOS transistor 318. At the same time, word line signal WL is at logic high, and NMOS transistor 320 is turned on. Because NMOS transistor 314 is always turned on, precharged dummy bit line DBL is discharged through NMOS transistors 318 and 314. When the voltage on dummy bit line DBL drops below a flipping point, control circuit 306 generates a clock signal and the sense amplifier 112 is triggered. Therefore, the sense amplifier 112 is now triggered not by control signal CTRL, but rather, by the clock signal generated by control circuit 306, which represents control signal CTRL delayed by the process of discharging dummy bit line DBL. Because tracking cell 304 has a structure similar to memory cell 104, the process of discharging dummy bit line DBL resembles the discharging process of bit lines BL or BL′ of memory cells 104. At the same time, control signal CTRL or a signal synchronized to control signal CTRL is used, without delay, to select and activate one of memory cells 104.
As discussed above, the tracking circuit 302 is used to control the timing delay from the moment the wordline WL is turned on to the moment the sense amplifier 112 is triggered. It is important that the tracking circuit 302 provide a timing delay for triggering the sense amplifier 112 that closely tracks the actual time required to discharge the bit line BL or BL′ associated with the selected memory cell 104. For example, if the delay is too short, it may cause a read failure because the read margin of memory device 100 will be below the differential voltage required to correctly read out the bit content of the memory cell 104 when the sense amplifier 112 is triggered. Conversely, if the delay is too long, it may hurt performance because the read margin of memory device 100 may be significantly higher than the differential voltage required to correctly read out the bit content of the memory cell 104 when the sense amplifier 112 is triggered, resulting in unnecessary power consumption, slower operating speeds, etc.
The time required to discharge the precharged bit line BL or BL′ is determined by the memory bit cell read current (Iread) of the memory device 100. Similarly, the time period required to discharge the precharged dummy bit line DBL, and hence, the timing delay before the sense amplifier 112 is triggered, depends on the drive current of the tracking circuit 302 (also referred to herein as the “tracking current”). There are several conventional techniques for correlating the tracking current of the tracking circuit 302 to the read current Iread of the memory device 100 in an attempt to achieve a desired read margin, each of which has associated drawbacks. In a first approach (the “single cell based” approach), the tracking current is adjusted by fabricating a given number of tracking cells 304 into the tracking circuit 302. Each additional tracking cell 304 in the conventional tracking circuit 302 proportionally increases the tracking current. So, for example, if a tracking circuit 302 includes one tracking cell 304 to provide a tracking current of 1× the read current Iread (read as 1 “times” the read current), a second tracking cell 304 will increase the tracking current to 2× the read current Iread, a third tracking cell 304 will increase the tracking current to 3× the read current Iread, and so on. Under this single cell based approach, however, each tracking cell's 304 random variation is so large in the latest process technology node (e.g., 65 nm and later), that it can no longer accurately track the average of the read current Iread in a real bitcell array. The tracking circuit 302 may also not be laid out in a true array like a real bitcell. This causes the tracking circuit 302 to be printed differently from the real bitcell array in later process technology nodes, leading to poor tracking or even hard failures. Further, the tracking current cannot achieve a current resolution of less than Iread, only one or multiples thereof.
In a second approach (the “logic based” approach), the size of the transistors of each tracking cell 304 is controlled to generate a predetermined current. Here, the tracking current and associated time period for discharging the precharged dummy bit line DBL is preset to correspond to the expected time required to discharge the bit line BL or BL′ associated with the selected memory cell 104. Even though this logic based approach can compensate for random device variations by using large width and/or length dimensions for the transistors of tracking cell 304 or using multiple devices to average out random variation, it does not track the read current Iread because it has different dimension parameters, threshold voltages, etc., from the real bitcell array transistors.